The present invention relates in general to diagnosing and debugging complementary logic circuit designs, and in particular to a system and method for ensuring that a complementary condition is maintained at the output of a complementary logic circuit. Still more particularly, the present invention relates to a system and method that correct an illegal non-complementary condition at the output of a complementary logic circuit, thereby avoiding the unpredictability and uncertainty that result from a non-complementary output, thus rendering the defective circuit fully functional.
As electronic circuit geometries decrease, testing for manufacturing defects becomes increasingly difficult. Many defects can be detected during manufacturing tests. However, some defects, such as resistive shorts between nets, resistive open contacts or excessive transistor leakage, cause only subtle effects that may not cause logical failure during an initial manufacturing test, but will cause failures at a later time. Quiescent power supply current (IDDq) testing has been utilized in the past to detect some of these subtle defects, but in deep sub-micron technologies, normal leakage currents are sufficiently high that it is becoming impossible to detect and identify small amounts of extra current caused by a defect.
Burn-in testing has been utilized in the past to accelerate early-life failures, but today""s deep sub-micron technologies are less capable of tolerating the high voltage and temperature conditions utilized in burn-in testing. These trends mean that electronic circuit initial quality and long-term reliability are becoming more difficult to assure, thus forming a need for improved methods of defect detection and error correction to improve initial quality, and to make circuits more fault tolerant in operation.
As processor speeds climb, circuit designers are challenged to achieve higher circuit speeds to accommodate the demand. Techniques such as dynamic logic are suitable for such applications, but are susceptible to performance degradation due to subtle design and manufacturing defects such as noise coupling, charge sharing, and high leakage. Furthermore, debugging dynamic logic is a complex and costly task. Consequently, fast static logic families are becoming more prevalent in the industry today to counteract the difficult design issues that arise in dynamic logic. Also, with the advent of Silicon-On-Insulator (SOI) technologies, with its relatively low capacitive loading and the ability to increase the number of devices in series (xe2x80x9cstack heightxe2x80x9d), static pass-gate logic is becoming very competitive with dynamic logic in circuit speed. In previous BULK CMOS technologies, the traditional limit on series N-type MOSFETs, commonly referred to in the art as xe2x80x9cnfetsxe2x80x9d, (the combination of transistors I1 and I3 or I1 and I4 of FIG. 1) has been two to three. However, in the newer SOI technologies, the limit on series nfets is climbing rapidly, and has already exceeded six. This trend is made possible by two advantageous characteristics of SOI technology: the device threshold dependency on the source-body voltage is removed; and the device diffusion capacitance is lowered by more than 66%.
Many of the fast static pass-gate logic families that are being utilized are complementary in nature, meaning that they produce both true and complement output signals, and circuit input signals are provided in both true and complement form. Examples of such families are Double Pass-transistor Logic (DPL), Differential Cascode Voltage Switch with Pass-Gate (DCVSPG), Complementary Pass-Transistor Logic (CPL), etc.
CPL circuits may be further categorized as belonging to one of two sub-classes: standard and cross-coupled. FIG. 1A depicts a prior art three way XOR/XNOR standard CPL circuit 100, while FIG. 1B illustrates a sample three way XOR/XNOR cross-coupled CPL circuit 150. Note in FIG. 1A that standard CPL circuit 100 utilizes small pmos feedback devices 110 and 112 from XOR output 102 and XNOR output 104 to internal node 106 and internal node 108 (TREE_T/TREE_C). Feedback devices 110 and 112 serve to draw the internal nodes 106 and 108 to full rail (up to VDD from VDD-VT). However, note that cross-coupled CPL circuit 150, of FIG. 1B, utilizes similar pmos devices 110 and 112, connected to complementary internal nodes 106 and 108 (TREE_T/TREE_C), which serve not only to draw the internal nodes full-rail but also increases circuit performance.
Note that in complementary logic circuits 100 and 150 of FIGS. 1A and 1B, input signals A 114 and A_ 116 are logical complements of each other, as are signal pairs B/B_ and C/C13. CPL, DCVSPG, and DPL circuits operate differentially. That is, when the input signals force one output high, the associated complementary output is forced low.
However, when a defect occurs in manufacturing or if a defect appears during circuit use, these outputs may no longer be complementary. When this happens, the circuits downstream of this defective circuit no longer see complementary input signals. These xe2x80x9cillegalxe2x80x9d input states can cause floating nodes (high-impedance, Z state) or value contention (1 and 0 driving onto a net simultaneously, for example) which will produce unpredictable circuit behavior. Thus, such a defect may not be detected during manufacturing testing. For example, if the A/A_ input signals in FIG. 1B are simultaneously at a non-complementary 0/0 state due to a defect in the circuit producing signals A/A13, nets TREE_T and TREE_C may be floating (undriven, high impedance) except for cross-coupled pfet devices 110 and 112. The values that will emerge at nodes 106 and 108 are unpredictable, thus making XOR output 102 and XNOR output 104 unpredictable. Likewise, if input signals A/A_ are simultaneously at a non-complementary 1/1 state due to a defect, nodes 106 and 108 (TREE_T and TREE_C) will be driven by contending high and low voltage values regardless of the values on the B and C input signals. The resultant voltages on nodes 106 and 108 may be at some value between the high and low voltage states for logic 1 and 0, thus causing complementary XOR/XNOR outputs 102 and 104 to be unpredictable. Most defects that cause an incorrect value at a single output of a complementary pass-gate circuit family will cause unpredictable behavior in downstream circuits, and are thus difficult to detect and identify during testing.
It would therefore be desirable to be able to correct an illegal non-complementary output from a complementary logic circuit during diagnostic testing. Further, it would be desirable to provide a system for selectively decoupling one transistor tree within a complementary logic circuit and utilize the other tree to ensure a complementary condition at the output of a complementary logic circuit. Such a system, if implemented, would be useful by ensuring that a defect in a complementary logic circuit that would normally cause a non-complementary output may be more effectively traced and corrected.
It is therefore one object of the present invention to provide a system and method for diagnosing and debugging complementary logic circuits.
It is another object of the present invention to provide a system and method for ensuring that a complementary condition is maintained at the output of a complementary logic circuit.
It is yet another object of the present invention to provide a system and method for correcting an illegal non-complementary condition at the output of a complementary logic circuit, thereby avoiding the unpredictability and uncertainty that result from a non-complementary output.
Some or all of the foregoing objects may be achieved in one embodiment of the present invention as is now described. A system within a complementary logic circuit having a true tree and a complement tree, for correcting an illegal non-complementary output caused by a defect in either tree is disclosed. A complementary logic circuit has a true tree for producing a true signal and a complement tree for producing a complement signal. The true signal is utilized to generate a true output signal from the complementary logic circuit and the complement signal is utilized to generate a complement output signal from the complementary logic circuit. Multiplexing means within the true and complement trees are utilized to selectively replace the true (complement) signal with the complement (true) signal within the true (complement) tree, such that the complement (true) tree is utilized to correct the occurrence of a proscribed non-complementary condition the output of the complementary logic circuit to diagnose a defect during diagnostic testing or to override a, defect during normal runtime operation.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.